Temperature Aware Vlsi Placement Algorithm using Genetic Algorithm

Placement is a key step in VLSI physical design cycle. With aggressive scaling if VLSI to Very Deep submicron level lead to higher power density which lead to generation on non uniform thermal map and hotspots. This scenario represent an important challenge in VLSI physical design to generate a layout that distribute temperature uniformly while optimizing traditional metrics like area, power and interconnect wire length. In this work a genetic algorithm based placement algorithm is proposed to that optimize temperature along with area and wire length.